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esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 1/51 2x15w stereo / 1x30w mono digital audio amplifier with eq functions and sub-woofer pwm out features z 16/18/20/24-bits input with i 2 s, left-alignment and right-alignment data format z psnr & dr(a-weighting) loudspeaker: 98db (psnr), 108db (dr) @24v z multiple sampling frequencies (fs) 32khz / 44.1khz / 48khz and 64khz / 88.2khz / 96khz and 128khz / 176.4khz / 192khz z system clock = 64x, 128x, 192x, 256x, 384x, 512x, 576x, 768x, 1024x fs 64x~1024x fs for 32khz / 44.1khz / 48khz 64x~512x fs for 64khz / 88.2khz / 96khz 64x~256x fs for 128khz / 176.4khz / 192khz z supply voltage 3.3v for digital circuit 12v~24v for loudspeaker driver z loudspeaker output power for 24v 10w x 2ch into 8 ? @0.2% thd+n for stereo 15w x 2ch into 8 ? @0.25% thd+n for stereo 20w x 1ch into 4 ? @0.25% thd+n for mono 30w x 1ch into 4 ? @0.3% thd+n for mono z sound processing including 8 bands parametric eq volume control (+24db~-103db, 0.5db/step), dynamic range control 3d surround sound channel mixing automatic zero-detection mute bass/treble tone control bass management crossover filter dc-blocking high-pass filter z anti-pop design z over-temperature protection z i 2 c control interface with selectable device address z support hardware and software reset z internal pll z subwoofer pwm output z under-voltage shutdown z short-circuit protection applications z cd and dvd z tv audio z car audio z boom-box z mp3 docking systems z powered speaker z wireless audio description AD82586 is a digital audio amplifier capable of driving a pair of 8 ? , 10w or a single 4 ? , 20w speaker operating at 24v supply without external heat-sink or fan requirement. it?s also capable of driving a pair of 8 ? , 15w or a single 4 ? , 30w speaker operating at a 24v supply with proper cooling method. AD82586 can provide advanced audio processing capabilities, such as volume control, 8 eq bands, audio mixing, 3d surround and dynamic range control(drc).these functions are fully programmable via a simple i 2 c control interface. robust protection circuits are provided to protect AD82586 from damage due to accidental erroneous operating condition. AD82586 is more tolerant to noise and pvt (process, voltage, and temperature) variation than the analog class-ab or class-d audio amplifier counterpart implemented by analog circuit design. AD82586 is pop free during instantaneous power switch because of its built-in, robust anti-pop circuit. the output stage is flexibly configurable for stereo or mono applications. in addition, AD82586 provides a sub-woofer pwm output port for the increasingly popular 2.1 channel applications. the programmable audio bass content of this subwoofer pwm output port can drive an external, low cost digital amplifier power stage (such as esmt?s ad9256h, ad92580, ..). furthermore, it is possible to use three pieces of AD82586 to realize 5.1 channels for home theater applications.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 2/51 pin assignment pin description pin name type description characteristics 1 vddla p left channel supply a 2 n.c. nc 3 n.c. nc 4 n.c. nc 5 n.c. nc 6 pll i pll enable, low active schmitt trigger ttl input buffer 7 mclk i master clock input schmitt trigger ttl input buffer 8 clk_out o clock output from pll ttl output buffer 9 dgnd p digital ground 10 dvdd p digital power 11 def i default volume setting (1:un-mute ; 0:mute) schmitt trigger ttl input buffer 12 sdata i serial audio data input schmitt trigger ttl input buffer 13 cfg0 i stereo/mono configuration pin (1:stereo ; 0: mono) schmitt trigger ttl input buffer 14 cfg1 i sub-woofer pwm output enable, high active schmitt trigger ttl input buffer
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 3/51 15 lrcin i left/right clock input (fs) schmitt trigger ttl input buffer 16 bclk i bit clock input (64fs) schmitt trigger ttl input buffer 17 pd i power down, low active schmitt trigger ttl input buffer 18 error o error status, low active open-drain output 19 reset i reset, low active schmitt trigger ttl input buffer 20 sa0 i i 2 c select address 0 schmitt trigger ttl input buffer 21 sa1 i i 2 c select address 1 schmitt trigger ttl input buffer 22 suba o sub-woofer pwm output a 23 subb o sub-woofer pwm output b 24 scl i i 2 c serial clock input schmitt trigger ttl input buffer 25 sda i/o i 2 c bi-directional serial data schmitt trigger ttl input buffer 26 dgnd p digital ground 27 dvdd p digital power 28 lrex i left/right channel exchange schmitt trigger ttl input buffer 29 sub_sdatao o sub-woofer serial audio data output 30 n.c. nc 31 n.c. nc 32 n.c. nc 33 test_1 o reserved pin for testing purpose 34 test_2 o reserved pin for testing purpose 35 n.c. nc 36 vddra p right channel supply a 37 ra o right channel output a 38 n.c. nc 39 gndra p right channel ground 40 gndrb p 41 rb o right channel output b 42 vddrb p right channel supply b 43 vddlb p left channel supply b 44 lb o left channel output b 45 gndlb p 46 gndla p left channel ground 47 n.c. nc 48 la o left channel output a
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 4/51 functional block diagram sa1 input interface i2c control interface pcm to pwm loudspeaker driver l r bclk sdata lrcin error audio signal processing sdm cfg1 reset pd pll internal system clock pll logic interface sa0 sda scl mclk cfg0 lrex suba subb sub_ sdatao ordering information product id package packing / mpq comments AD82586-le48nay e-lqfp-48l 7x7 mm 2.5k units / small box (250 units / tray, 10 trays / small box) green available package package type device no. ja ( /w) jt ( /w) jc ( /w) exposed thermal pad 7x7 48l e-lqfp AD82586 27.4 1.33 6.0 yes (note1) note 1.1: the thermal pad is located at the botto m of the package. to optimize thermal performance, soldering the thermal pad to the pcb?s ground plane is suggested. note 1.2: ja is measured on a room temperature (t a =25 ), natural convection environment test board, which is constructed with a thermally efficient, 4-layers pcb (2s2p). the measurement is tested using the jedec51-5 thermal measurement standard. note 1.3: jc represents the heat resistance for the heat flow between the chip and the package?s top surface. note 1.4: jt represents the heat resistance for the heat fl ow between the chip and the exposed pad?s center. absolute maximum ratings symbol parameter min max units dvdd supply for digital circuit 0 3.6 v vddl/r supply for driver stage 0 30 v v i input voltage -0.3 3.6 v t stg storage temperature -65 150 o c t a ambient operating temperature 0 70 o c
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 5/51 recommended operating conditions digital characteristics symbol parameter min typ max units v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v v oh high-level output voltage 2.4 v v ol low-level output voltage 0.4 v c i input capacitance 6.4 pf general electrical characteristics symbol parameter condition min typ max units i pd (hv) pvdd supply current during power down pvdd=24v 10 ua i pd (lv) dvdd supply current during power down dvdd=3.3v 10 ua junction temperature for driver shutdown 160 o c 40 o c 2.8 v uv l under voltage enabled (for dvdd) 2.7 v static drain-to-source on-state resistor, pmos 295 m rds-on static drain-to-source on-state resistor, nmos pvdd=24v, id=500ma 185 m l(r) channel over-current prot ection (note 2) pvdd=24v 5 a i sc mono channel over-circuit protec tion (note 2) pvdd=24v 10 a note 2: loudspeaker over-current protection is on ly effective when loudspea ker drivers are properly connected with external lc filters. please refe r to the application circuit example for recommended lc filter configuration. marking information AD82586 line 1 : logo line 2 : product no. line 3 : tracking code line 4 : date code symbol parameter typ units dvdd supply for digital circuit 3.15~3.45 v vddl/r supply for driver stage 10~26 v t a ambient operating temperature 0~70 o c pin1 dot esmt AD82586 tracking code date code
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 6/51 application circuit example for stereo
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 7/51 application circuit example for stereo (economic type, moderate emi suppression)
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 8/51 application circuit example for mono
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 9/51 application circuit example for st ereo with subwoofer pwm output
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 10/51 electrical characteristics and specifications for loudspeaker z stereo output condition: dvdd =3.3v, vddl=vddr=24v, f s =48khz, load=8 with passive lc lowpass filter (l=22 h with r dc =0.12 , c=470nf); input is 1khz sinewave. volu me is 0db unless otherwise specified. symbol parameter condition input level min typ max units rms output power (thd+n=10% ) +8db volume -6db 35 w p o (note 9) rms output power (thd+n=1%) +8db volume -7.8db 28 w thd+n total harmonic distortion + noise p o =21.8w -1db 0.37 % snr signal to noise ratio(note 8) p o =21.8w -1db 98 db dr dynamic range(note 8) -60db 108 db psrr power supply rejection ratio -60db 60 db channel separation 1w @1khz -1db 60 db efficiency 85 note 8: measured with a-weighting filter. note 9: thermal dissipation is limited by package ty pe and pcb design. the external heat-sink or system cooling method should be adopted for maximum power output. total harmonic distortion + nois e vs. output power (stereo)
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 11/51 total harmonic distortion + noise vs. frequency (stereo) spectrum at peak snr (stereo) spectrum at -60db signal input level (stereo)
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 12/51 efficiency (stereo) efficiency vs. output power (stereo) 0 10 20 30 40 50 60 70 80 90 100 0 10203040506070 2ch output power(w) efficiency(%) 12v 15v 18v 24v efficiency (stereo) for power saving mode efficiency vs. output power (stereo) 0 10 20 30 40 50 60 70 80 90 100 0 10203040506070 2ch output power(w) efficiency(%) 24v power saving mode 24v
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 13/51 electrical characteristi cs and specifications for loudspeaker (cont.) z mono output condition: dvdd= 3.3v, vddl=vddr=24v, f s =48khz, load=4 with passive lc lowpass filter (l=10 h with r dc =0.12 , c=470nf); input is 1khz sinewave. volu me is 0db unless otherwise specified. symbol parameter condition input level min typ max units rms output power (thd+n=10%) +8db volume -5.8db 69 w p o (note 9) rms output power (thd+n=1%) +8db volume -7.8db 56 w thd+n total harmonic distortion + noise p o =44w -1db 0.4 % snr signal to noise ratio(note 8) p o =44w -1db 97 db dr dynamic range(note 8) -60db 106 db psrr power supply rejection ratio -60db 60 db efficiency 86 note 8: measured with a-weighting filter. note 9: thermal dissipation is limited by package ty pe and pcb design. the external heat-sink or system cooling method should be adopted for maximum power output. total harmonic distortion + no ise vs. output power (mono)
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 14/51 total harmonic distortion + noise vs. frequency (mono) spectrum at peak snr (mono) spectrum at -60db signal input level (mono)
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 15/51 efficiency (mono) efficiency vs. output power (mono) 0 10 20 30 40 50 60 70 80 90 100 0 10203040506070 output power(w) efficiency(%) 12v 15v 18v 24v 4 mono efficiency (mono) for power saving mode efficiency vs. output power (mono) 0 10 20 30 40 50 60 70 80 90 100 0 102030405060 output power(w) efficiency(%) 24v power saving mode 24v
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 16/51 interface configuration z i 2 s z left-alignment z right-alignment z system clock timing z timing relationship (using i 2 s format as an example) lrcin bclk sdata left right msb msb t lr t bl t lb t bcc t ds t dh t bch t bcl
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 17/51 symbol parameter min typ max units t lr lrcin period (1/f s ) 10.41 31.25 s t bl bclk rising edge to lrcin edge 50 ns t lb lrcin edge to bclk rising edge 50 ns t bcc bclk period (1/64f s ) 162.76 488.3 ns t bch bclk pulse width high 81.38 244 ns t bcl bclk pulse width low 81.38 244 ns t ds sdata set-up time 50 ns t dh sdata hold time 50 ns z i 2 c timing t f t hd;sta t low t r t hd;dat t su;dat t f t high t su;sta t hd;sta t su;sto t r t buf ssr ps standard mode fast mode parameter symbol min. max. min. max. unit scl clock frequency f scl 0 100 0 400 khz hold time for repeated start condition t hd,sta 4.0 --- 0.6 --- s low period of the scl clock t low 4.7 --- 1.3 --- s high period of the scl clock t high 4.0 --- 0.6 --- s setup time for repeated start condition t su;sta 4.7 --- 0.6 --- s hold time for i 2 c bus data t hd;dat 0 3.45 0 0.9 s setup time for i 2 c bus data t su;dat 250 --- 100 --- ns rise time of both sda and sdl signals t r --- 1000 20+0.1cb 300 ns fall time of both sda and sdl signals t f --- 300 20+0.1cb 300 ns setup time for stop condition t su;sto 4.0 --- 0.6 --- s bus free time between stop and the next start condition t buf 4.7 --- 1.3 --- s capacitive load for each bus line c b 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl 0.1v dd --- 0.1v dd --- v noise margin at the high level for each connected device (including hysteresis) v nh 0.2v dd --- 0.2v dd --- v
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 18/51 operation description z operation modes (i) without i 2 c control the default settings, bass, treble, eq, volume, d rc, pll, subwoofer bandwi dth, ?, and sub-woofer gain are applied to register table content when using AD82586 without i 2 c control. the more information about default settings, please refer to the high lighted column of register table section. (ii) with i 2 c control when using i 2 c control, user can program suitable parameters into AD82586 for their specific applications. please refer to the register table section to get the more detail. z reset when the reset pin is lowered, AD82586 will clear the stor ed data and reset the register table to default values. AD82586 will exit reset state at the 256 th mclk cycle after the reset pin is raised to high. z power down control AD82586 has a built-in volume fade-in/fade-out design for pd/mute function. the relative pd timing diagrams for loudspeakers are shown below. AD82586 will detect pd pin once an lrcin cycle. when AD82586 detects 9 cons ecutive zeros, it will execute a fade-out procedure. the volume level will be decreased to - db in several lrcin cycles. once the fade-out procedure is finished, AD82586 will turn off the power stages, clock signal s (for digital circuits) and current (for analog circuits). after pd pin is pulled low, AD82586 requires 256 lrcin clocks to finish the forementioned work before entering power down state. users can not program AD82586 during power down state. also all settings in the registers will remain intact unless dvdd is removed.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 19/51 when AD82586 detect 9 c onsecutive ones from pd pin, the pd function will be disabled and a fade-in procedure is then executed. if the pd signal is remo ved during the fade-out proc edure (above, right figure), AD82586 will still execute the fade-in pr ocedure. in addition, AD82586 will establish the analog circuits? bias current and send the clock signals to digital circuits. afterwards, AD82586 will return to its normal status. z internal pll ( pll ) AD82586 has a built-in pll internally. when the exter nal mclk clock is high quality enough, you can bypass the pll function by pulling the pll pin high. otherwise, the internal pll wi th an external reference mclk is highly recommended. z self-protection circuits AD82586 has built-in protection circuits including ther mal, short-circuit and under-voltage detection circuits. (i) when the internal junction temperature is higher than 160 , power stages will be turned off and AD82586 will return to normal operation once the temperature drops to 120 . the temperature values may vary around 10%. (ii) the short-circuit protection circuit protects the output stage when the wires which are connected to loudspeakers are shorted to each other or gnd/vd d. for normal 24v operations, the current flowing through the power stage will be less than 5a for stereo configuration or less than 10a for mono configuration. otherwise, the shor t-circuit detectors may pull the error pin to dgnd, disabling the output stages. when the over-temperature or sh ort-circuit condition occurs, the open-drain error pin will be pulled low and latched into error state. once the over-temperature or short-circuit conditi on is removed, AD82586 will exit error state when one of the following conditions is met: (1) reset pin is pulled low, (2) pd pin is pulled low, (3) master mute is enabled through the i 2 c interface. (iii) once the dvdd voltage is lower than 2.7v, AD82586 will turn off its loudspeaker power stages and cease the operation of digital processing circuits . when dvdd becomes larger than 2.8v, AD82586 will return to normal operation.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 20/51 z anti-pop design AD82586 will generate appropriate control signals to s uppress pop sounds during initial power on/off, power down/up, mute, and volume level changes. z power on sequence hereunder is ad82581?s power on sequence. please note t hat we suggested users set def pin at low state initially, and than give a de-mute command via i 2 c when the whole system is stable. pvdd dvdd mclk reset scl sda de-mute note. set def pin at low state initially z 3d surround sound AD82586 provides the virtual surround sound technology with greater separation and depth voice quality for stereo signals.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 21/51 z output configuration AD82586 can be configured to stereo or mono mode by the pin of cfg0. if the sub-woofer pwm signal is required on your applications, you can select it from the pin of cfg1 to enable it. cfg1 cfg0 configuration mode 0 0 mono 0 1 stereo 1 1 stereo with subwoofer output configuration figures:
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 22/51 i 2 c-bus transfer protocol z introduction AD82586 employs i 2 c-bus transfer protocol. two wires, serial data and serial clock carry information between the devices connected to the bus. each dev ice is recognized by a unique 7-bit address and can operate as either a transmitter or a receiver. the mast er device initiates a data transfer and provides the serial clock on the bus. AD82586 is always an i 2 c slave device. z protocol ? start and stop condition start is identified by a high to low transition of the sda signal.. a start condition must precede any command for data transfer. a stop is identified by a low to high transition of the sda signal. a stop condition terminates communication between AD82586 and the master device on the bus. in both start and stop, the scl is stable in the high state. ? data validity the sda signal must be stable during the high period of the clock. the high or low change of sda only occurs when scl signal is low. AD82586 samples t he sda signal at the rising edge of scl signal. ? device addressing the master generates 7-bit address to recogniz e slave devices. when AD82586 receives 7-bit address matched with 0110x0y (where x and y can be selected by external sa0 and sa1 pins, respectively), AD82586 will acknowledge at the 9 th bit (the 8 th bit is for r/w bit). the bytes following the device identification address are for AD82586 internal sub-addresses. ? data transferring each byte of sda signaling must consist of 8 c onsecutive bits, and the byte is followed by an acknowledge bit. data is transferred with msb firs t, as shown in the figure below. in both write and read operations, AD82586 supports both single-byte and multi-byte transfers. refer to the figure below for detailed data-transferring protocol.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 23/51 register table the AD82586?s audio signal processing data flow is shown below. users can control these functions by programming appropriate settings in the register table. in this section, the register table is summarized first. the definition of each register follows in the next section. address name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] 0x00 sctl1 if[2] if[1] if[0] reserved lrexc 0x01 sctl2 reserved fs[1] fs[0] pmf[3] pmf[2] pmf[1] pmf[0] 0x02 sctl3 en_clko reserved mmute cm1 cm2 cm3 0x03 mvol mv[7] mv[6] mv[5] mv[4] mv[3] mv[2] mv[1] mv[0] 0x04 c1vol c1v[7] c1v[6] c1v[5] c1v[4] c1v[3] c1v[2] c1v[1] c1v[0] 0x05 c2vol c2v[7] c2v[6] c2v[5] c2v[4] c2v[3] c2v[2] c2v[1] c2v[0] 0x06 c3vol c3v[7] c3v[6] c3v[5] c3v[4] c3v[3] c3v[2] c3v[1] c3v[0] 0x07 btone reserved btc[4] btc[3] btc[2] btc[ 1] btc[0] 0x08 ttone reserved ttc[4] ttc[3] ttc[2] ttc[1] ttc[0] 0x09 auto1 reserved xo[3] xo[2] xo[1] xo[0] 0x0a sctl4 srbp bte reserved zde eql psl dspb hpb 0x0b c1cfg reserved c1drcbp c1hpfbp c1vbp 0x0c c2cfg reserved c2drcbp c2hpfbp c2vbp 0x0d c3cfg reserved c3drcbp c3hpfbp c3vbp
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 24/51 0x0e lar la[3] la[2] la[1] la[0] lr[3] lr[2] lr[1] lr[0] 0x0f latrt lat[3] lat[2] lat[1] lat[0] lrt[3] lrt[ 2] lrt[1] lrt[0] 0x10 erdly reserved 0x11 sctl5 reserved sw_rstb reserved dis_mclk_det qt_en pwm_sel 0x12 hvuv reserved hv_uvsel [3] hv_uvsel [2] hv_uvsel [1] hv_uvsel [0] 0x13 zdcfg reserved zd_level[1] zd_level[0] zd_gain[1] zd_gain[0] 0x14 cfaddr reserved cfa[6] cfa[5] cfa[4] cfa[3] cfa[2] cfa[1] cfa[0] 0x15 a1cf1 c1b[23] c1b[22] c1b[21] c1b[20] c1b[19] c1b[18] c1b[17] c1b[16] 0x16 a1cf2 c1b[15] c1b[14] c1b[13] c1b[12] c1b[11] c1b[10] c1b[ 9] c1b[8] 0x17 a1cf3 c1b[7] c1b[6] c1b[5] c1b[4] c1b[3] c1b[2] c1b[1] c1b[0] 0x18 a2cf1 c2b[23] c2b[22] c2b[21] c2b[20] c2b[19] c2b[18] c2b[17] c2b[16] 0x19 a2cf2 c2b[15] c2b[14] c2b[13] c2b[12] c2b[11] c2b[10] c2b[ 9] c2b[8] 0x1a a2cf3 c2b[7] c2b[6] c2b[5] c2b[4] c2b[3] c2b[2] c2b[1] c2b[0] 0x1b b1cf1 c3b[23] c3b[22] c3b[21] c3b[20] c3b[19] c3b[18] c3b[17] c3b[16] 0x1c b1cf2 c3b[15] c3b[14] c3b[13] c3b[12] c3b[11] c3b[10] c3b[ 9] c3b[8] 0x1d b1cf3 c3b[7] c3b[6] c3b[5] c3b[4] c3b[3] c3b[2] c3b[1] c3b[0] 0x1e b2cf1 c4b[23] c4b[22] c4b[21] c4b[20] c4b[19] c4b[18] c4b[17] c4b[16] 0x1f b2cf2 c4b[15] c4b[14] c4b[13] c4b[12] c4b[11] c4b[10] c4b[ 9] c4b[8] 0x20 b2cf3 c4b[7] c4b[6] c4b[5] c4b[4] c4b[3] c4b[2] c4b[1] c4b[0] 0x21 a0cf1 c5b[23] c5b[22] c5b[21] c5b[20] c5b[19] c5b[18] c5b[17] c5b[16] 0x22 a0cf2 c5b[15] c5b[14] c5b[13] c5b[12] c5b[11] c5b[10] c5b[ 9] c5b[8] 0x23 a0cf3 c5b[7] c5b[6] c5b[5] c5b[4] c5b[3] c5b[2] c5b[1] c5b[0] 0x24 cfud reserved ra r1 wa w1 0x25 fdcfg reserved 0x26 mbist reserved 0x27 status reserved 0x28 pwm_ct rl reserved 0x29 tm_ctr l reserved 0x2a qt_sw_le vel reserved qt_sw_level [4] qt_sw_level [3] qt_sw_level [2] qt_sw_level [1] qt_sw_level [0]
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 25/51 detail description for register note that the highlighted columns are default values of these tables. if there is no highlighted value, the default setting of this bit is determined by the external pin. z address 0 : state control 1 AD82586 supports multiple serial data input formats including i 2 s, left-alignment and right-alignment. these formats are selected by users via bit7~bit5 of address 0. the lef t/right channels can be exchanged to each other by programming to address 0/bit0, lrexc. bit name description value function 000 i 2 s 16-24 bits 001 left-alignment 16-24 bits 010 right-alignment 16 bits 011 right-alignment 18 bits 100 right-alignment 20 bits b[7:5] if[2:0] input format 101 right-alignment 24 bits b[4] reserved b[3] reserved b[2] reserved b[1] reserved 0 no exchanged b[0] lrexc left/right (l/r) channel exchanged 1 l/r exchanged z address 1 : state control 2 AD82586 has a built-in pll which can be bypassed by pulling the pll pin high. when pll is bypassed, AD82586 only supports 1024x, 512x and 256x mclk/fs rati o for fs is 32/44.1/48khz, 64/88.2/96khz, and 128/176.4/192khz respectively. when pll is enabled, mu ltiple mclk/fs ratios are supported. detail setting is shown in the following table. bit name description value function b[7:6] reserved 00 32/44.1/48khz 01 64/88.2/96khz b[5:4] fs[1:0] sampling frequency 1x 128/176.4/192khz
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 26/51 multiple mclk/fs ratio setting table bit name description value b[5:4]=00 b[5:4]=01 b[5:4]=1x 0000 1024x 512x 256x 0001 64x 64x 64x 0010 128x 128x 128x 0011 192x 192x 192x 0100 reset default (256x) reset default (256x) reset default (256x) 0101 384x 384x 0110 512x 512x 0111 576x 1000 768x b[3:0] pmf[3:0] mclk/fs setup when pll is not bypassed 1001 1024x reserved reserved z address 2 : state control 3 AD82586 has mute function including master mute and channel mute. when master mute is enabled, all 3 processing channels are muted. user can mute these 3 channels individually by channel mute. when the mute function is enabled or disabled, the f ade-out or fade-in proc ess will be initiated. bit name description value function 0 disabled b[7] en_clk_ out pll clock output 1 enabled b[6] reserved b[5] reserved b[4] reserved 0 all channel not muted b[3] mute master mute 1 all channel muted 0 ch1 not muted b[2] cm1 channel 1 mute 1 only ch1 muted 0 ch2 not muted b[1] cm2 channel 2 mute 1 only ch2 muted 0 ch3 not muted b[0] cm3 channel 3 mute 1 only ch3 muted
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 27/51 z address 3 : master volume control AD82586 supports both master-volume (address 3) and channel-volume control (address 4, 5 and 6) modes. both volume control settings range from +12db ~ -103db and 0.5db per step. note that the master volume control is added to the individual channel volume contro l as the total volume control. for example, if the master volume level is set at, level a (in db unit) and t he channel volume level is set at level b (in db unit), the total volume control setting is equal to level a plus with level b. -103db Q total volume ( level a + level b ) Q +24db. bit name description value function 00000000 +12.0db 00000001 +11.5db 00000010 +11.0db U U 00010111 +0.5db 00011000 0.0db 00011001 -0.5db U U 11100110 -103.0db 11100111 - db U U bit[7:0] mv[7:0] master volume 11111111 - db z address 4 : channel 1 volume bit name description value function 00000000 +12.0db 00000001 +11.5db 00000010 +11.0db U U 00010111 +0.5db 00011000 0.0db 00011001 -0.5db U U 11100110 -103.0db 11100111 - db U U bit[7:0] c1v[7:0] channel1 volume 11111111 - db
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 28/51 z address 5 : channel 2 volume bit name description value function 00000000 +12.0db 00000001 +11.5db 00000010 +11.0db U U 00010111 +0.5db 00011000 0.0db 00011001 -0.5db U U 11100110 -103.0db 11100111 - db U U bit[7:0] c2v[7:0] channel2 volume 11111111 - db z address 6 : channel 3 volume bit name description value function 00000000 +12.0db 00000001 +11.5db 00000010 +11.0db U U 00010111 +0.5db 00011000 0.0db 00011001 -0.5db U U 11100110 -103.0db 11100111 - db U U bit[7:0] c3v[7:0] channel3 volume 11111111 - db
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 29/51 z address 7/8 : bass/treble tone boost and cut last two sets of eq can be programmed as bass/treble tone boost and cut. when, register with address-10, bit-6, bte is set to high, the eq-7 and eq-8 will pe rform as bass and treble respectively. the -3db corner frequency of bass is 250hz, and treble is 7khz. the gain range for both filters is +12db ~ -12db with 1db per step. bit name description value function b[7:5] reserved 00000 +12db ? ? 00100 +12db 00101 +11db 00110 +10db ? ? 01110 +2db 01111 +1db 10000 0db 10001 -1db 10010 -2db ? ? 11010 -10db 11011 -11db 11100 -12db ? ? b[4:0] btc[4:0] / ttc[4:0] the gain setting of boost and cut 11111 -12db
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 30/51 z address 9 : bass management crossover frequency the AD82586 provides bass management crossover frequency selection. a 1 st order high-pass filter (channel 1 and 2) and a 2 nd order low-pass filter (channel 3) at selected frequency are performed. bit name description value function b[7:4] reserved 0000 80hz 0001 100hz 0010 120hz 0011 140hz 0100 160hz 0101 180hz 0110 200hz 0111 220hz 1000 240hz 1001 260hz 1010 280hz 1011 300hz 1100 320hz 1101 340hz 1110 360hz b[3:0] xo[3:0] bass management crossover frequency 1111 ---
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 31/51 z address 10 : state control 4 the AD82586 provides this register to configure th e audio processing enable or bypass and channel link. the dc blocking high pass and eq can be enabled of bypass. during the link bit is set to logic high, the post-scale scaling factor or eq for all of channel ca n be mapped to channel-1. this provides much simple audio sound processing setup. an automatic zeros detecti on mute is built-in. if a channel receives 2048 consecutive zero value sample, then this ch annel is muted when the function is enabled. bit name description value function 0 surround enable b[7] srbp surround bypass 1 surround bypass 0 bass/treble disable b[6] bte bass/treble selection enable 1 bass/treble enable b[5] reserved. 0 zero detection disable b[4] zde automatic zero detection mute enable 1 zero detection enable 0 each channel uses individual eq b[3] eql eq link 1 use channel-1 eq 0 each channel uses individual post-scale b[2] psl post-scale link 1 use channel-1 post-scale 0 pre-scale and eq enable b[1] dspb pre-scale and eq bypass 1 pre-scale and eq bypass 0 hpf enable b[0] hpb dc blocking hpf bypass 1 hpf bypass
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 32/51 z address 11, 12 and 13 : channel configuration registers the AD82586 can configure each channel to enable or by pass eq and channel volume and select the limiter set. address 11 and 12; where x=1 or 2 bit name description value function b[7] reserved b[6] reserved b[5] reserved b[4] reserved 0 channel pc enable b[3] cxpcbp channel x power clipping bypass 1 channel pc bypass 0 channel x drc enable b[2] cxdrcbp channel x drc bypass 1 channel x drc bypass 0 channel x hpf enable b[1] cxhpfbp channel x bass management hpf bypass 1 channel x hpf bypass 0 channel x?s master volume operation b[0] cxvbp channel x volume bypass 1 channel x?s master volume bypass address 13 bit name description value function b[7] reserved b[6] reserved b[5] reserved b[4] reserved 0 channel pc enable b[3] c3pcbp channel 3 power clipping bypass 1 channel pc bypass 1 channel3 drc bypass b[2] c3drcbp channel 3 drc bypass 1 channel3 drc bypass 0 channel3 lpf enable b[1] c3hpfbp channel 3 bass management lpf bypass 1 channel3 lpf bypass 0 channel3 master volume operation b[0] c3vbp channel 3 volume bypass 1 channel3 master volume bypass
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 33/51 z address 14 : drc limiter attack/release rate the AD82586 defines a set of limiter. the attack/release rates are defined as following table. bit name description value function 0000 3 db/ms 0001 2.667 db/ms 0010 2.182 db/ms 0011 1.846 db/ms 0100 1.333 db/ms 0101 0.889 db/ms 0110 0.4528 db/ms 0111 0.2264 db/ms 1000 0.15 db/ms 1001 0.1121 db/ms 1010 0.0902 db/ms 1011 0.0752 db/ms 1100 0.0645 db/ms 1101 0.0563 db/ms 1110 0.0501 db/ms b[7:4] la[3:0] drc attack rate 1111 0.0451 db/ms 0000 0.5106 db/ms 0001 0.1371 db/ms 0010 0.0743 db/ms 0011 0.0499 db/ms 0100 0.0360 db/ms 0101 0.0299 db/ms 0110 0.0264 db/ms 0111 0.0208 db/ms 1000 0.0198 db/ms 1001 0.0172 db/ms 1010 0.0147 db/ms 1011 0.0137 db/ms 1100 0.0134 db/ms 1101 0.0117 db/ms 1110 0.0112 db/ms b[3:0] lr[3:0] drc release rate 1111 0.0104 db/ms
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 34/51 z address 15 : drc limiter attack/release threshold the AD82586 defines a set of limiter. the attack/rel ease thresholds are defined as following table. bit name description value function 0000 -31 db 0001 -29 db 0010 -27 db 0011 -25 db 0100 -23 db 0101 -21 db 0110 -19 db 0111 -17 db 1000 -16 db 1001 -15 db 1010 -14 db 1011 -13 db 1100 -12 db 1101 -10 db 1110 -7 db b[7:4] lat[3:0] drc attack threshold 1111 -4 db 0000 infinite 0001 -38 db 0010 -36 db 0011 -33 db 0100 -31 db 0101 -30 db 0110 -28 db 0111 -26 db 1000 -24 db 1001 -22 db 1010 -20 db 1011 -18 db 1100 -15 db 1101 -12 db 1110 -9 db b[3:0] lrt[3:0] dr c release threshold 1111 -6 db
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 35/51 z address 17 : state control 5 bit name description value function b[7] reserved b[6] reserved 0 reset b[5] sw_rstb software reset 1 normal operation b[4] reserved b[3] reserved 0 enable mclk detect circuit b[2] dis_mclk_det disable mclk detect circuit 1 disable mclk detect circuit 0 disable b[1] qt_en power saving mode 1 enable 0 qua-ternary b[0] pwm_sel pwm modulation 1 ternary z address 18 : pvdd under voltage selection the AD82586 defines five sets of under voltage level. bit name description value function 0000 8.2v 0001 9.7v 0011 13.2 v 0100 15.5 v 1100 19.5 v b[3:0] hv_uv sel uv detection level others 9.7v
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 36/51 z address 19 : zero detection level selection this register is to define zero detection level selection. bit name description value function b[7] reserved b[6] reserved b[5] reserved b[4] reserved 00 signal = 0 01 signal <-110db 10 signal < -100db b[3:2] zd_level[1:0] zero detection level 11 signal < -90db 00 x1/8 01 x1/4 10 x1/2 b[1:0] zd_gain[1:0] zero detection gain level 11 mute z address 20~36 : user-defined coefficients registers an on-chip ram in AD82586 stores user-defined eq and mi xing coefficients. the content of this coefficient ram is indirectly accessed via coeffi cient registers, which consist of one base address register (address 20), five sets of registers (address 21 to 35) of three consecutive 8-bit entries for each 24-bit coefficient, and one control register (address 36) to control access of the coefficients in the ram.. address 20 bit name description value function b[7] reserved b[6:0] cfa[6:0] coefficient ram base address 0000000 address 21, a1cf1 bit name description value function b[7:0] c1b[23:16] top 8-bits of coefficients a1
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 37/51 address 22, a1cf2 bit name description value function b[7:0] c1b[15:8] middle 8-bits of coefficients a1 address 23, a1cf3 bit name description value function b[7:0] c1b[23:16] bottom 8-bits of coefficients a1 address 24, a2cf1 bit name description value function b[7:0] c2b[23:16] top 8-bits of coefficients a2 address 25, a2cf2 bit name description value function b[7:0] c2b[15:8] middle 8-bits of coefficients a2 address 26, a2cf3 bit name description value function b[7:0] c2b[7:0] bottom 8-bits of coefficients a2 address 27, b1cf1 bit name description value function b[7:0] c3b[23:16] top 8-bits of coefficients b1 address 28, b1cf2 bit name description value function b[7:0] c3b[15:8] middle 8-bits of coefficients b1
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 38/51 address 29, b1cf3 bit name description value function b[7:0] c3b[7:0] bottom 8-bits of coefficients b1 address 30, b2cf1 bit name description value function b[7:0] c4b[23:16] top 8-bits of coefficients b2 address 31, b2cf2 bit name description value function b[7:0] c4b[15:8] middle 8-bits of coefficients b2 address 32, b2cf3 bit name description value function b[7:0] c4b[7:0] bottom 8-bits of coefficients b2 address 33, a0cf1 bit name description value function b[7:0] c5b[23:16] top 8-bits of coefficients a0 address 34, a0cf2 bit name description value function b[7:0] c5b[15:8] middle 8-bits of coefficients a0 address 35, a0cf3 bit name description value function b[7:0] c5b[7:0] bottom 8-bits of coefficients a0
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 39/51 address 36, cfrw bit name description value function b[7:4] reserved 0 read complete b[3] ra enable of reading a set of coefficients from ram 1 read enable 0 read complete b[2] r1 enable of reading a single coefficients from ram 1 read enable 0 write complete b[1] wa enable of writing a set of coefficients to ram 1 write enable 0 write complete b[0] w1 enable of writing a single coefficient to ram 1 write enable
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 40/51 z address 42 : power saving mode switching level if the pwm exceeds the programmed switching power level (default 26*40ns), the modulation algorithm will change from quaternary into power saving mode. it results in higher power efficiency during larger power output operations. if the pwm drops below the programm ed switching power level, the modulation algorithm will change back to quaternary modulation. bit name description value function b[7] reserved b[6] reserved b[5] reserved 11111 62 11110 60 : : 01111 30 01110 28 01101 26 : : 00010 4 00001 4 b[4:0] qt_sw_level switching level 00000 4 total harmonic distortion + noise vs. output power 0.04 2 0.06 0.08 0.2 0.3 0.5 0.7 1 % 2 20 345678910 w quaternary switching level 20 switching level 30 switching level 40 switching level 46 24v, 8 ?
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 41/51 the procedure to read/write coeffici ent(s) from/to ram is as followings: read a single coefficient from ram: 1. write 7-bis of address to i2c address-20 2. write 1 to r1 bit in address-36 3. read top 8-bits of coefficient in i2c address-21 4. read middle 8-bits of coefficient in i2c address-22 5. read bottom 8-bits of coefficient in i2c address-23 read a set of coefficients from ram: 1. write 7-bits of address to i2c address-20 2. write 1 to ra bit in address-36 3. read top 8-bits of coefficient a1 in i2c address-21 4. read middle 8-bits of coefficient a1 in i2c address-22 5. read bottom 8-bits of coefficient a1 in i2c address-23 6. read top 8-bits of coefficient a2 in i2c address-24 7. read middle 8-bits of coefficient a2 in i2c address-25 8. read bottom 8-bits of coefficient a2 in i2c address-26 9. read top 8-bits of coefficient b1 in i2c address-27 10. read middle 8-bits of coefficient b1 in i2c address-28 11. read bottom 8-bits of coefficient b1 in i2c address-29 12. read top 8-bits of coefficient b2 in i2c address-30 13. read middle 8-bits of coefficient b2 in i2c address-31 14. read bottom 8-bits of coefficient b2 in i2c address-32 15. read top 8-bits of coefficient a0 in i2c address-33 16. read middle 8-bits of coefficient a0 in i2c address-34 17. read bottom 8-bits of coefficient a0 in i2c address-35 write a single coefficient from ram: 1. write 7-bis of address to i2c address-20 2. write top 8-bits of coefficient in i2c address-21 3. write middle 8-bits of coefficient in i2c address-22 4. write bottom 8-bits of coefficient in i2c address-23 5. write 1 to w1 bit in address-36
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 42/51 write a set of coefficients from ram: 1. write 7-bits of address to i2c address-20 2. write top 8-bits of coefficient a1 in i2c address-21 3. write middle 8-bits of coefficient a1 in i2c address-22 4. write bottom 8-bits of coefficient a1 in i2c address-23 5. write top 8-bits of coefficient a2 in i2c address-24 6. write middle 8-bits of coefficient a2 in i2c address-25 7. write bottom 8-bits of coefficient a2 in i2c address-26 8. write top 8-bits of coefficient b1 in i2c address-27 9. write middle 8-bits of coefficient b1 in i2c address-28 10. write bottom 8-bits of coefficient b1 in i2c address-29 11. write top 8-bits of coefficient b2 in i2c address-30 12. write middle 8-bits of coefficient b2 in i2c address-31 13. write bottom 8-bits of coefficient b2 in i2c address-32 14. write top 8-bits of coefficient a0 in i2c address-33 15. write middle 8-bits of coefficient a0 in i2c address-34 16. write bottom 8-bits of coefficient a0 in i2c address-35 17. write 1 to wa bit in address-36 note that: the read and write operation on ram coefficient s works only if lrcin (pin-15) switching on rising edge. and, before each writing operation, it is necessar y to read the address-36 to confirm whether ram is writable current in first. if the l ogic of w1 or wa is high, the coefficient writing is prohibited.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 43/51 z user-defined equalizer the AD82586 has built-in 8-bands parametric eq for each channel. each eq, users can program suitable coefficients via i 2 c control interface to get the required audio band frequency response. the transfer function of eq is: the data format of 2?s complement binary code for eq coef ficient is 4.20. i.e., 4-bits for integer (msb is sign bit) and 20-bits for mantissa. the each coefficient range is from 0x800000 (-8) to 0x7fffff (+7.999999046325684). these coefficients are stored in user defined ram and are referenced in following manner: where x and y represents the number of channel and the band number of eq biquard, respectively. by default, all user-defined f ilters are path-through where all coefficients are set to 0, except the a0 is set to 0x100000 (represents 1). z mixer the AD82586 provides mixers to generate the extra audio source from input left/right channels. the coefficients of mixers are defined in range from 0x 800000 (-1) to 0x7fffff (0.9999998808). the function block diagram is as following: m12 m11 m22 m21 m32 m31 lch rch sub l r 2 2 1 1 2 2 1 1 0 1 ) ( ? ? ? ? + + + + = z b z b z a z a a z h 2 2 1 1 2 2 1 1 0 0 b chxeqyb b chxeqyb a chxeqya a chxeqya a chxeqya ? = ? = = = =
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 44/51 z pre-scale the AD82586 provides a multiplication stage for each c hannel for the purpose of scaling signal prior to eq. the pre-scale is realized with a 24-bit sig ned fractional multiplier, with 0x800000=-1 and 0x7fffff=0.9999998808. the scaling factor for this multiply is loaded into ram using the same i2c registers as the biquad coefficients and mixing scaling factors. by default, the pre-scale factors are set to 0x7fffff. all channels can use the channel-1 pre- scale factor by setting the biquad-scale link. z post-scale the AD82586 provides an additional multiplication before interpolation stage and the distortion compensation on each channel. the postscale is realized with a 24-bit signed fractional multiplier, with 0x800000=-1 and 0x7fffff=0.9999998808. the scaling factor for this multiplication is loaded into ram using the same i2c registers as the biquad coefficients and mixing scaling factors. by default, the pre-scale factors are set to 0x7fffff. all channels can use the ch annel-1 post-scale factor by setting the post-scale link. z power clipping the ad83586 provides power clipping to avoid suddenly large signal that destroy loud speaker. the power clipping level is programmed that using 24 bits to define it. 0x200000 means output voltage will be limited at pvdd. 0x100000 means output voltage will be limited at 0.5*pvdd. ad83586 provide 3 sets of power clipping for each channel.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 45/51 z the user defined ram the contents of user defined ram are represented in following table. address name coefficient default 0x00 ch1eq1a1 0x000000 0x01 ch1eq1a2 0x000000 0x02 ch1eq1b1 0x000000 0x03 ch1eq1b2 0x000000 0x04 channel-1 eq1 ch1eq1a0 0x100000 0x05 ch1eq2a1 0x000000 0x06 ch1eq2a2 0x000000 0x07 ch1eq2b1 0x000000 0x08 ch1eq2b2 0x000000 0x09 channel-1 eq2 ch1eq2a0 0x100000 0x0a ch1eq3a1 0x000000 0x0b ch1eq3a2 0x000000 0x0c ch1eq3b1 0x000000 0x0d ch1eq3b2 0x000000 0x0e channel-1 eq3 ch1eq3a0 0x100000
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 46/51 address name coefficient default 0x0f ch1eq4a1 0x000000 0x10 ch1eq4a2 0x000000 0x11 ch1eq4b1 0x000000 0x12 ch1eq4b2 0x000000 0x13 channel-1 eq4 ch1eq4a0 0x100000 0x14 ch1eq5a1 0x000000 0x15 ch1eq5a2 0x000000 0x16 ch1eq5b1 0x000000 0x17 ch1eq5b2 0x000000 0x18 channel-1 eq5 ch1eq5a0 0x100000 0x19 ch1eq6a1 0x000000 0x1a ch1eq6a2 0x000000 0x1b ch1eq6b1 0x000000 0x1c ch1eq6b2 0x000000 0x1d channel-1 eq6 ch1eq6a0 0x100000 0x1e ch1eq7a1 0x000000 0x1f ch1eq7a2 0x000000 0x20 ch1eq7b1 0x000000 0x21 ch1eq7b2 0x000000 0x22 channel-1 eq7 ch1eq7a0 0x100000 0x23 ch1eq8a1 0x000000 0x24 ch1eq8a2 0x000000 0x25 ch1eq8b1 0x000000 0x26 ch1eq8b2 0x000000 0x27 channel-1 eq8 ch1eq8a0 0x100000 0x28 reserved 0x29 reserved 0x2a reserved 0x3b reserved 0x2c reserved
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 47/51 address name coefficient default 0x2d ch2eq1a1 0x000000 0x2e ch2eq1a2 0x000000 0x2f ch2eq1b1 0x000000 0x30 ch2eq1b2 0x000000 0x31 channel-2 eq1 ch2eq1a0 0x100000 0x32 ch2eq2a1 0x000000 0x33 ch2eq2a2 0x000000 0x34 ch2eq2b1 0x000000 0x35 ch2eq2b2 0x000000 0x36 channel-2 eq2 ch2eq2a0 0x100000 0x37 ch2eq3a1 0x000000 0x38 ch2eq3a2 0x000000 0x39 ch2eq3b1 0x000000 0x3a ch2eq3b2 0x000000 0x3b channel-2 eq3 ch2eq3a0 0x100000 0x3c ch2eq4a1 0x000000 0x3d ch2eq4a2 0x000000 0x3e ch2eq4b1 0x000000 0x3f ch2eq4b2 0x000000 0x40 channel-2 eq4 ch2eq4a0 0x100000 0x41 ch2eq5a1 0x000000 0x42 ch2eq5a2 0x000000 0x43 ch2eq5b1 0x000000 0x44 ch2eq5b2 0x000000 0x45 channel-2 eq5 ch2eq5a0 0x100000 0x46 ch2eq6a1 0x000000 0x47 ch2eq6a2 0x000000 0x48 ch2eq6b1 0x000000 0x49 ch2eq6b2 0x000000 0x4a channel-2 eq6 ch2eq6a0 0x100000
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 48/51 address name coefficient default 0x4b ch2eq7a1 0x000000 0x4c ch2eq7a2 0x000000 0x4d ch2eq7b1 0x000000 0x4e ch2eq7b2 0x000000 0x4f channel-2 eq7 ch2eq7a0 0x100000 0x50 ch2eq8a1 0x000000 0x51 ch2eq8a2 0x000000 0x52 ch2eq8b1 0x000000 0x53 ch2eq8b2 0x000000 0x54 channel-2 eq8 ch2eq8a0 0x100000 0x55 reserved 0x56 reserved 0x57 reserved 0x58 reserved 0x59 reserved 0x5a channel-1 mixer1 m11 0x7fffff 0x5b channel-1 mixer2 m12 0x000000 0x5c channel-2 mixer1 m21 0x000000 0x5d channel-2 mixer2 m22 0x7fffff 0x5e channel-3 mixer1 m31 0x400000 0x5f channel-3 mixer2 m32 0x400000 0x60 channel-1 prescale c1prs 0x7fffff 0x61 channel-2 prescale c2prs 0x7fffff 0x62 channel-1 postscale c1pos 0x7fffff 0x63 channel-2 postscale c2pos 0x7fffff 0x64 channel-3 postscale c3pos 0x7fffff 0x65 channel-1 power clipping pc1 0x200000 0x66 channel-2 power clipping pc2 0x200000 0x67 channel-3 power clipping pc3 0x200000
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 49/51 package dimensions 7mm x 7mm 48-pin e-lqfp b d2 e2 e d1 d e1 e dimensions in millimeters symbols min. nom. max. a 1.60 a1 0.05 0.15 b 0.17 0.22 0.27 d 9.00 bsc d1 7.00 bsc d2 4.5 5.0 5.5 e 9.00 bsc e1 7.00 bsc e2 4.5 5.0 5.5 e 0.50 bsc l 0.45 0.60 0.75 l1 1.00 bsc 0 3.5 7 a a 1 l1 l
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 50/51 revision history revision date description 0.1 2010.11.26 original 0.2 update measuring data 0.3 2011.09.20 1) changed pvdd range from 12v~24v to 10v~26v. 2) changed pvdd absolute maximum rating from 26v to 30v. 3) updated the application circ uit that the snubber circuit can be removed while the pvdd <=18v for stereo. 4) added the application circuit for economic type, moderate emi suppression. 5) added power on sequence flow. 6) updated mpq description.
esmt/emp preliminary AD82586 elite semiconductor memory technology inc./elite micropower inc . publication date: sep. 2011 revision: 0.3 51/51 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to c hange the products or specification in this document without notice. the information contained herein is pres ented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its us e. no license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inhe rently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against in jury, damage, or loss from such failure, should be provided by the custom er when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human live s or cause physical injury or property damage. if products descri bed here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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